For decades, process and design scaling has triggered the adoption of transformative test solutions. About twenty years ago, when at-speed test became a de-facto requirement, on-chip compression ...
As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin ...
IC designers now have a powerful weapon in the struggle against rising test costs: commercially available EDA solutions that provide fast and effective means to implement scan compression on-chip. By ...
SAN MATEO, Calif. — Design-for-test tool vendor SynTest Technologies Inc. is putting the finishing touches on a test-data volume compaction technology for scan-based design. VirtualScan will help ...
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